1. Field of the Invention
This invention relates to semiconductor nanoelectronics devices and more particularly relates to a cylindrical-shaped nanotube field effect transistor.
2. Description of the Related Art
Increasing the computational capability of electronic devices often depends on increasing the number of transistors in an integrated circuit. Moore's Law suggests that the number of transistors in an integrated circuit doubles approximately every two years. Continuing to advance electronic devices at the rate suggested by Moore's Law has resulting in scaling the transistor dimensions such that a transistor occupies smaller areas, which allows higher densities of transistors in an integrated circuit.
Physical scaling of the transistor can result in changes in device physics. For example, as the gate length of a transistor decreases below 50 nanometers short channel effects (SCE) become more pronounced as well as device variability, gate control, and leakage power dissipation control becomes challenging. Additionally, understanding of quasi-ballistic to ballistic transportation is more difficult as the devices scale in size. Conventionally, transistors have been built on silicon-on-insulator (SOI)-based or ultra-thin body (UTB)-based multi-gate devices to present better electrostatic control and reduced parasitic short channel effects.
Volume inversion effects have been employed to improve performance in multi-gate devices. Volume inversion effects are introduced when the thickness of the semiconductor film is reduced below the inversion layer thickness induced by the multiple gates. For example, in a double gate SOI FET volume inversion is achieved when the silicon (Si) film is thinner than the inversion layer thickness induced by the two gates. In volume inversion, an inversion layer is formed at the interfaces of the silicon film and throughout the silicon film. When a device operates in volume inversion carriers are distributed throughout the silicon film. The volume inversion presents a significant number of advantages, such as enhancement of the number of minority carriers, an increase in drain current and transconductance, decrease of low frequency noise, and a reduction in hot-carrier effects.
However, SOI-based and UTB-based multi-gate transistors are difficult to manufacture because of the high aspect ratio feature etching, cost of SOI or UTB devices, dopant diffusion and uniform profile control with angled implantation for high aspect ratio devices, contact engineering, and position control.